As the size and complexity of integrated circuits increases, so do the pressures on designing clock trees for the circuits. Designers face an increasing number of logic gates, registers, register banks etc which need to deliver, act on and receive suitably timed signals.
There are various automated techniques for designing clock trees based on a circuit which has been defined in terms of its logical design and which is to be implemented physically. That is, a clock tree synthesis tool forms parts of a physical design process. One such tool is the Astro clock tree synthesis tool sold by Synopsys, which receives information concerning the logic circuit including an sdc (Synopsys Design Constraint) file which contains timing constraints in TCL format.
FIG. 1 generally illustrates how this tool is used in the physical design process. A cell placement tool 8, responsible for placing cells in a circuit layout, receives information from a Netlist 11 together with constraints that the Netlist must meet in the form of an sdc file 12 and operates to place logic circuits such as gates, registers, etc. The Netlist 11 and sdc file 12 hold data and criteria defining a circuit to be synthesized, which is used to load a database (not shown). The output of the placement tool 8 is supplied to a clock tree synthesis tool 10 which constructs clock trees based on the cell layout. The clock tree synthesis tool 10 also receives timing constraints from the sdc file 12. The clock tree synthesis tool updates the database which is used for other design processes such as routing etc, represented by block 13. The output of the design process is a file 3 which can be supplied to manufacture the circuit.
The tool 10 supports an optimization process illustrated in FIG. 1. That is, it implements a timing check after placement and routing by the Astro tool 10 and determines whether or not there is any opportunity to improve the timing of the circuit by applying useful skew 16. Useful skew is a well known concept in the design of circuits, and involves altering delays on critical paths to improve the timing of the circuit. This can involve increasing the delay on a path between a start point and an end point, in dependence on the timing of other associated paths. Reference numeral 16 denotes the step of applying useful skew in the clock tree synthesis process by feeding back timing information to the clock tree synthesis tool 10.
However, conventional techniques have many difficulties associated with it. The options for skewing may be restricted after initial placement of the logic circuits, or the initial placement and any modified placement may be sub-optimal because the placement tool 8 has initially tried to meet a timing constraint of zero skew.